1. Field
Various exemplary embodiments of the present invention relate to a semiconductor device and, more particularly, to a semiconductor device with a transistor and a method of fabricating the same.
2. Description of the Related Art
As transistors in a semiconductor device are scaled down to improve performance, the gate dielectric layer gets thinner and gate leakage increases. To address this concern, the gate dielectric layer is replaced with a high-k material having a dielectric constant greater than the dielectric constant of silicon dioxide (SiO2). The high-k material may include a metal oxide containing hafnium, zirconium, etc. As the high-k material is introduced, a Fermi level pinning effect is caused by the contact between the high-k material and a polysilicon gate electrode. The Fermi level pinning effect is a characteristic of the interface between the polysilicon gate electrode and the metal oxide, and it increases the threshold voltage of a transistor.
Recently, a gate structure including a high-k material and a metal gate electrode have been utilized to address the Fermi level pinning effect. However, during the CMOS device fabrication process it may be difficult to form a metal gate electrode having an N-type work function and a P-type work function, which require an appropriate threshold voltage Vt for each transistor. Although a metal gate electrode having an appropriate work function for each transistor is formed, the work function of the gate structure may fluctuate due to the materials of the gate dielectric layer that contact the metal gate electrode, and various other factors originating from the gate stack formation process, such as an etch process and a high-temperature thermal process.